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Products / Logic TPI

Logic TPI — EntropyDFT™

We built a better test point inserter (TPI): a software tool that inserts snippets of hardware into a chip design to fix test problems. Our patented solution uses better mathematics for a competitive advantage.

How it works Results View fact sheetPDF
01 — How it works

Better mathematics decides where test points go

Method

Information theory

Entropy tells us where a design hides information from the tester. Test points go where they buy the most observability.

Method

Digital frequency spectrum analysis

Signals are read as spectra, not coin flips. Competitors use simple probability theory and no frequency analysis at all.

Method

Correlation-aware testability measures

More accurate testability measures that account for signal correlation, which competitors' measures ignore.

50 Tournaments per insertion run

We use a series of 10–50 tournaments to insert test points. It makes better decisions and keeps compute time low.

02 — Where it sits

EntropyDFT™ runs after logic synthesis

What it gives you
0199.98% fault coverage on 0.71% additional chip area — competitors use 4%.
02Test hardware small enough that timing and the power grid stay where your team put them.
037.638% fewer tests, so vectors are shorter and tester time drops.
04Low compute time: 10–50 tournaments decide the insertion, not an exhaustive search.
05Drops into the flow you already run, with Cadence-verified layout results.
Flow
RTL Chip Layout logic synthesis (turn RTL into Logic Gates) path delay balancing power-grid adjustment static timing closure (prove timing is correct) functional verification (prove logic matches RTL) EntropyDFT™(fix test) 20–40+ iterations
03 — Results

Drastic test cost reduction

0.71%
Test hardware chip area

Reduced area → fabrication line cost saving. The biggest factor.

7.638%
Fewer tests

Reduced number of tests → test equipment saving.

0.02%
Untested faults

Reduced % untested faults → labor cost saving.

Compute time saving

Lowers computer time across the insertion run.

Labor cost saving

Fewer memory modifications to the chip.

Source: direct chip layout experiments with our test point inserter using Cadence tools.

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