Products / Future Products

RTL TPI, in development

Inserting test points at the register-transfer level, before logic synthesis, so test never fights timing and power for the rest of the schedule.

01 — Why RTL

20–40+ iterations become two

Done with Logic TPI
20–40 months
20–40+ iterations

Test point insertion happens after synthesis, so it disturbs timing closure and the power grid — and the design goes round again. Test points add extra circuit delay where they are inserted.

Done with RTL TPI
4–6 months
2–3 iterations

Test points enter the RTL, then synthesis, path delay balancing, timing closure, verification and power-grid adjustment run once on a design that already has its test hardware.

RTL TPI flow
RTL Chip Layout RTL test point insertion(fix test) logic synthesis (turn RTL into Logic Gates) path delay balancing power-grid adjustment static timing closure (prove timing is correct) functional verification (prove logic matches RTL) 2-3 iterations
Stock photography.
02 — Recognition · RTL TPI

Our RTL TPI work has been accepted into this year's ITC conference

The International Test Conference paper covers the RTL insertion method and the measured effect on iteration count. Read the announcement on the blog.

Future roadmap
01RTL test point insertion for path delay fault models.
02RTL test point insertion for stacked chiplet 3D wiring.
03Entropy measures carried up from gates to RTL constructs, inside RTL TPI.
Interested in an early evaluation of RTL TPI?
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