Spectral Chip Test at ITC 2026 for its RTL TPI work!
Our paper on register-transfer-level test point insertion has been accepted into this year's International Test Conference.
The work moves test point insertion ahead of logic synthesis. Today, inserting test points into a gate-level netlist disturbs timing and power, so the design goes back through path delay balancing, static timing closure, functional verification and power-grid adjustment — 20 to 40 or more iterations, and 20 to 40 months of schedule.
Inserting at RTL means synthesis sees the test hardware from the start. In our experiments the flow settles in two to three iterations, four to six months, with the coverage our Logic TPI product already delivers.
The method rests on the same mathematics as the rest of our tools: entropy to find where the design hides information from the tester, and digital frequency spectrum analysis to know which faults a pattern set can actually excite.
Details on the product timeline are on the Future Products page.