EntropyDFT Overview: Test Point & Scan Insertion ToolBased on U.S. Patent # 8,164,345 and Provisional U.S. Patent # 63/413,393

Capabilities- Estimates lost faults during testing, gives the reason for their loss, and shows what to change to make the faults testable • Tested on > 300 Verilog designs of up to 4.6 million gates - Optionally inserts test points • Dramatially reduces # test vectors • Further improves test coverage • Better results than competing solutions- Patented method based on Information Theory, Machine Learning, and Statistical Analysis - Entropy “warms up” the circuit by logic simulating it with random digital noise • Computes P (1), P (0), Entropy (information content), % time signal unknown, % time in X/Z state, and Signal activity for all signals • Statistially unbiases probabilities - Statistics used in 2 ways: • Estimate the number of untestable faults • Recommend order for inserting test points Automatic X/Z Blocker Insertion - Entropy™ automatially backtraces from same D flip-flops that catch X/Z's in each tournament • Finds X/Z generator (at the earliest point in circuit) - Chooses X/Z generators to block in each tournament • Based on untestable fault loss estimation • Uses logic 0/1/X/Z values from logic simulator • Far faster than Sequential ATPG -- one EntropyXZ pass is equivalent to hundreds of Sequential ATPG runs

Automatic Test Point Insertion Methods- Automatic mixed TP and scan flip-flop insertion in full/partial-scan designs using X/Z analysis and entropy (information flow)- Notouch Patterns – name matching patterns to easily notouch parts of large designs • For decompressor/ompressor, BIST controller, scan chains, memory models, Central Test Controller, etc. - Backtraces from scan flops catching X/Z signals to find problem source in combinational logic • Inserts Test Point on X/Z signal - Reports X/Z generators, sorted in inverse order by the number of untestable faults they cause